Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
As integrated circuits, and particularly memory integrated circuits, have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as memory size increases, the time which a memory integrated circuit (e.g., DRAM) emerging from a fabrication process line spends in testing increases as well. This increase incurs an additional cost on DRAM manufacturing. The testing cost can be very significant for the latest and largest memories. In addition, as more complex systems-on-a-chip devices proliferate, which integrate DRAM with other functions onto a single chip, and as newly designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to incorporate elaborate testing circuitry directly into these devices in order to adequately test them.
The incorporated testing circuitry is adapted to test two general areas of the integrated circuit, the memory elements, and the logic/processing elements. For example, in the case of integrated circuits which incorporate both memory and logic, there are usually two main areas which need to be tested, the memory block and the shadow logic surrounding the memory block.
The memory block is the circuit structure which stores the actual data, while the shadow logic is the surrounding gates and logic elements needed to interface the memory block with other external circuits. In order to adequately test the DRAM, both areas (e.g., the shadow logic and the memory block) need to be tested. However, in a typical prior art DRAM, the shadow logic is very hard to test independently with respect to the memory block.
In the prior art, the shadow logic (e.g., the logic gates surrounding the memory block) are particularly hard, if not impossible, to precisely test. The shadow logic is hard to test in isolation from the memory block in an efficient manner. Hence, the challenge presented by modern DRAM integrated circuits is that it is difficult to perform an isolated test on the DRAM memory block and an isolated test on the shadow logic. In accordance with the prior art, a built-in test circuit typically tests the memory block and ignores the shadow logic.
In the case of integrated circuits incorporating both memory and logic functions, where there is often no direct connection between external pins and the integrated memory, external testing using external devices can be even more difficult and even more imprecise. Direct access to the embedded memory may not exist. Consequently, to ensure the bits of the memory block are tested adequately, lengthy "test vectors" are required. Because of this, these types of integrated circuits are even more difficult to properly test.
Thus, what is needed is a method for testing the shadow logic without incurring a large silicon area penalty. What is needed is a system which allows an isolated test on the shadow logic and also allows an isolated test on the DRAM. What is further needed is a system to allow isolated testing without incurring excessive silicon area penalties. The present invention provides a novel solution to the above requirements.